Input buffers driven with single-ended signals, yet having differential outputs can be used, for instance, in signal processing where a signal must be transmitted over long distances with minimal signal degradation due to interference from external sources, i.e. noise. The differential output signal is produced to be output over two lines as a positive and negative form of the input signal. Because any signal noise would most likely affect both lines equally, the noise component may be removed from the signal by subtracting the two outputs.
One problem associated with input buffers driven with single-ended input signals is ensuring a balanced differential output. FIG. 1A illustrates a schematic of a conventional input buffer 100 depicted as an operational amplifier. The amplifier 100 receives an input voltage Vin at a positive terminal and a reference voltage Vref at a negative terminal. The amplifier 100 outputs differential outputs Vout+, Vout− based on the input voltage Vin. As shown in FIG. 1B, when the input buffer is used as a comparator, the input signal Vin received by the conventional input buffer 100 may oscillate around the reference voltage Vref. FIG. 1C shows the differential outputs Vout+, Vout− from the conventional input buffer 100. As shown, the outputs Vout+, Vout− are not balanced; i.e., Vout− should be the exact inverse of Vout+, such that the crossing points 150 of the two output signals Vout+, Vout− occur where if the output signals Vout+, Vout− were added, the net result would be zero.
FIG. 2 illustrates a circuit diagram of a conventional input buffer 200 that is driven with single-ended signals Vin and Vref and generates an unbalanced negative output signal Vout−. Input buffer 200 includes a first stage circuit 280 and a second stage circuit 290. The first stage circuit 280 includes a first input transistor 201 for receiving the input signal Vin at a gate terminal 201′, a second input transistor 202 for receiving a reference voltage Vref at a gate terminal 202′, first and second general feedback transistors 203, 204 having associated gates 203′, 204′, and third and fourth general feedback transistors 207, 208 with associated gates 207′, 208′. The gates 203′, 204′ of the first and second general feedback transistors 203, 204 are electrically connected to each other, and the gates 207′, 208′ of the third and fourth general feedback transistors 207, 208 are electrically connected to each other. Also, a drain terminal of each of the third and fourth general feedback transistors 207, 208 is respectively electrically connected to a source terminal of each of the first and second input transistors 201, 202. The first stage circuit 280 further includes an output node 209 at which positive output Vout+ is generated. The output node 209 is electrically connected to the drain terminal of the fourth general feedback transistor 208 and to the source terminal of the second input transistor 202. In addition, first stage circuit 280 includes a first connection node 220 which is connected to a drain terminal of the third general feedback transistor 207, to a source terminal of the first input transistor 201, to the gates 203′, 204′ of the first and second general feedback transistors 203, 204, and to the gates 207′, 208′ of the third and fourth general feedback transistors 207, 208.
Enable transistors 211, 212 may be connected between a power source Vcc and a source terminal of the third and fourth general feedback transistors 207, 208. The enable transistors 211, 212 receive an enable signal EN at a gate terminal 211′, 212′ to activate the first stage circuit 280.
The second stage circuit 290 includes a third input transistor 250 for receiving the output voltage Vout+ at a gate terminal 250′, fifth and sixth general feedback transistors 252, 253 having associated gates 252′, 253′, and seventh and eighth general feedback transistors 254, 255 with associated gates 254′, 255′. The gates 252′, 253′ of the fifth and sixth general feedback transistors 252, 253 are electrically connected to each other, and the gates 254′, 255′ of the seventh and eighth general feedback transistors 254, 255 are electrically connected to each other. Also, a drain terminal of the seventh general feedback transistor 254 is electrically connected to a source terminal of the third input transistor 250, and a drain terminal of the eighth general feedback transistor 255 is electrically connected to a source terminal of the sixth general feedback transistor 253. The second stage circuit 290 further includes an output node 256 at which negative output Vout− is generated. The output node 256 is electrically connected to the drain terminal of the eighth general feedback transistor 255 and to the source terminal of the sixth general feedback transistor 253. In addition, second stage circuit 290 includes a second connection node 260 which is connected to a drain terminal of the seventh general feedback transistor 254, to a source terminal of the third input transistor 250, to the gates 252′, 253′ of the fifth and sixth general feedback transistors 252, 253, and to the gates 254′, 255′ of the seventh and eighth general feedback transistors 254, 255.
Enable transistors 257, 258 may be connected between a power source Vcc and a source terminal of each of the third and fourth general feedback transistors 254, 255. The enable transistors 257, 258 receive an enable signal EN at a gate terminal 257′, 258′ to activate the second stage circuit 290.
The configuration of the conventional input buffer driven with single-ended signals and outputting only negative output signals generates unbalanced positive and negative output signals, such as that illustrated in FIG. 1C. Accordingly, there is a desire for a input buffer driven with single-ended signals that generates a better balanced differential output.